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fa600b88b1
revert [Texture_cache] Better memory handling for devices with lower memory allocations (#233) Means games like Minecraft Dungeons, Sea of Stars, Luigi Mansion 2, Astroneer, Alan Wake, etc are now playable. It also cleans up the recent abi.cpp and bindless texture commits a bit. Everything is in #ifdef ANDROID - The biggest change is CACHING_PAGEBITS = 12. Without that the way the buffercache grows and joins buffers can cause Android to run out of memory (as you end up with just one big buffer that needs to be copied every time it grows) Also patches up ffmpeg issues. Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/233 Co-authored-by: JPikachu <jpikachu.eden@gmail.com> Co-committed-by: JPikachu <jpikachu.eden@gmail.com> Had showed some regressions on devices with higher specifications, will be refined to return as a toggle in a later commit. Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/240
66 lines
2.3 KiB
C++
66 lines
2.3 KiB
C++
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class ShuffleMode : u64 {
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IDX,
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UP,
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DOWN,
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BFLY,
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};
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[[nodiscard]] IR::U32 ShuffleOperation(IR::IREmitter& ir, const IR::U32& value,
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const IR::U32& index, const IR::U32& mask,
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ShuffleMode shfl_op) {
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const IR::U32 clamp{ir.BitFieldExtract(mask, ir.Imm32(0), ir.Imm32(5))};
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const IR::U32 seg_mask{ir.BitFieldExtract(mask, ir.Imm32(8), ir.Imm32(5))};
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switch (shfl_op) {
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case ShuffleMode::IDX:
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return ir.ShuffleIndex(value, index, clamp, seg_mask);
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case ShuffleMode::UP:
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return ir.ShuffleUp(value, index, clamp, seg_mask);
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case ShuffleMode::DOWN:
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return ir.ShuffleDown(value, index, clamp, seg_mask);
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case ShuffleMode::BFLY:
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return ir.ShuffleButterfly(value, index, clamp, seg_mask);
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default:
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throw NotImplementedException("Invalid SHFL op {}", shfl_op);
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}
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}
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void Shuffle(TranslatorVisitor& v, u64 insn, const IR::U32& index, const IR::U32& mask) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg;
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BitField<30, 2, ShuffleMode> mode;
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BitField<48, 3, IR::Pred> pred;
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} const shfl{insn};
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const IR::U32 result{ShuffleOperation(v.ir, v.X(shfl.src_reg), index, mask, shfl.mode)};
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v.ir.SetPred(shfl.pred, v.ir.GetInBoundsFromOp(result));
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v.X(shfl.dest_reg, result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::SHFL(u64 insn) {
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union {
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u64 insn;
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BitField<20, 5, u64> src_a_imm;
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BitField<28, 1, u64> src_a_flag;
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BitField<29, 1, u64> src_b_flag;
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BitField<34, 13, u64> src_b_imm;
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} const flags{insn};
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const IR::U32 src_a{flags.src_a_flag != 0 ? ir.Imm32(static_cast<u32>(flags.src_a_imm))
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: GetReg20(insn)};
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const IR::U32 src_b{flags.src_b_flag != 0 ? ir.Imm32(static_cast<u32>(flags.src_b_imm))
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: GetReg39(insn)};
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Shuffle(*this, insn, src_a, src_b);
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}
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} // namespace Shader::Maxwell
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