Ryujinx/ARMeilleure/Decoders
Ficture Seven 2421186d97
Generalize tail continues (#1298)
* Generalize tail continues

* Fix DecodeBasicBlock

`Next` and `Branch` would be null, which is not the state expected by
the branch instructions. They end up branching or falling into a block
which is never populated by the `Translator`. This causes an assert to
be fired when building the CFG.

* Clean up Decode overloads

* Do not synchronize when branching into exit block

If we're branching into an exit block, that exit block will tail
continue into another translation which already has a synchronization.

* Remove A32 predicate tail continue

If `block` is not an exit block then the `block.Next` must exist (as
per the last instruction of `block`).

* Throw if decoded 0 blocks

Address gdkchan's feedback

* Rebuild block list instead of setting to null

Address gdkchan's feedback
2020-06-18 13:37:21 +10:00
..
Optimizations
Block.cs
Condition.cs
DataOp.cs
Decoder.cs
DecoderHelper.cs
InstDescriptor.cs
InstEmitter.cs
IntType.cs
IOpCode.cs
IOpCode32.cs
IOpCode32Alu.cs
IOpCode32AluBf.cs
IOpCode32AluReg.cs
IOpCode32AluUx.cs
IOpCode32BImm.cs
IOpCode32BReg.cs
IOpCode32Mem.cs
IOpCode32MemEx.cs
IOpCode32MemMult.cs
IOpCode32Simd.cs
IOpCode32SimdImm.cs
IOpCodeAlu.cs
IOpCodeAluImm.cs
IOpCodeAluRs.cs
IOpCodeAluRx.cs
IOpCodeBImm.cs
IOpCodeCond.cs
IOpCodeLit.cs
IOpCodeSimd.cs
OpCode.cs
OpCode32.cs
OpCode32Alu.cs
OpCode32AluBf.cs
OpCode32AluImm.cs
OpCode32AluImm16.cs
OpCode32AluMla.cs
OpCode32AluReg.cs
OpCode32AluRsImm.cs
OpCode32AluRsReg.cs
OpCode32AluUmull.cs
OpCode32AluUx.cs
OpCode32BImm.cs
OpCode32BReg.cs
OpCode32Exception.cs
OpCode32Mem.cs
OpCode32MemImm.cs
OpCode32MemImm8.cs
OpCode32MemLdEx.cs
OpCode32MemMult.cs
OpCode32MemReg.cs
OpCode32MemRsImm.cs
OpCode32MemStEx.cs
OpCode32Sat.cs
OpCode32Sat16.cs
OpCode32Simd.cs
OpCode32SimdBase.cs
OpCode32SimdBinary.cs
OpCode32SimdCmpZ.cs
OpCode32SimdCvtFI.cs
OpCode32SimdDupElem.cs
OpCode32SimdDupGP.cs
OpCode32SimdExt.cs
OpCode32SimdImm.cs
OpCode32SimdImm44.cs
OpCode32SimdLong.cs
OpCode32SimdMemImm.cs
OpCode32SimdMemMult.cs
OpCode32SimdMemPair.cs
OpCode32SimdMemSingle.cs
OpCode32SimdMovGp.cs
OpCode32SimdMovGpDouble.cs
OpCode32SimdMovGpElem.cs
OpCode32SimdReg.cs
OpCode32SimdRegElem.cs
OpCode32SimdRegElemLong.cs
OpCode32SimdRegLong.cs
OpCode32SimdRegS.cs
OpCode32SimdRev.cs
OpCode32SimdS.cs
OpCode32SimdSel.cs
OpCode32SimdShImm.cs
OpCode32SimdShImmNarrow.cs
OpCode32SimdSpecial.cs
OpCode32SimdSqrte.cs
OpCode32SimdTbl.cs
OpCode32System.cs
OpCodeAdr.cs
OpCodeAlu.cs
OpCodeAluBinary.cs
OpCodeAluImm.cs
OpCodeAluRs.cs
OpCodeAluRx.cs
OpCodeBfm.cs
OpCodeBImm.cs
OpCodeBImmAl.cs
OpCodeBImmCmp.cs
OpCodeBImmCond.cs
OpCodeBImmTest.cs
OpCodeBReg.cs
OpCodeCcmp.cs
OpCodeCcmpImm.cs
OpCodeCcmpReg.cs
OpCodeCsel.cs
OpCodeException.cs
OpCodeMem.cs
OpCodeMemEx.cs
OpCodeMemImm.cs
OpCodeMemLit.cs
OpCodeMemPair.cs
OpCodeMemReg.cs
OpCodeMov.cs
OpCodeMul.cs
OpCodeSimd.cs
OpCodeSimdCvt.cs
OpCodeSimdExt.cs
OpCodeSimdFcond.cs
OpCodeSimdFmov.cs
OpCodeSimdHelper.cs
OpCodeSimdImm.cs
OpCodeSimdIns.cs
OpCodeSimdMemImm.cs
OpCodeSimdMemLit.cs
OpCodeSimdMemMs.cs
OpCodeSimdMemPair.cs
OpCodeSimdMemReg.cs
OpCodeSimdMemSs.cs
OpCodeSimdReg.cs
OpCodeSimdRegElem.cs
OpCodeSimdRegElemF.cs
OpCodeSimdShImm.cs
OpCodeSimdTbl.cs
OpCodeSystem.cs
OpCodeT16.cs
OpCodeT16AluImm8.cs
OpCodeT16BReg.cs
OpCodeTable.cs
RegisterSize.cs
ShiftType.cs